Kanchan Manna; Jimson Mathew Design and Test Strategies for 2D/3D Integration for NoC-based Multicore Architectures 9783030313098

Варианты приобретения

Цена: 6097.00р.
Кол-во:
Наличие: Поставка под заказ. Есть в наличии на складе поставщика.
Склад Америка: Есть
При оформлении заказа до: 2026-06-01
Ориентировочная дата поставки: Июль
При условии наличия книги у поставщика.

Добавить в корзину

в Мои желания

Автор: Kanchan Manna; Jimson Mathew
Название: Design and Test Strategies for 2D/3D Integration for NoC-based Multicore Architectures
ISBN: 9783030313098
Издательство: Springer
Классификация:

Электроника

Схемы и компоненты

Архитектура и логическое построение вычислительных систем

Машинное зрение

ISBN-10: 3030313093
Обложка/Формат: Hardcover
Страницы: 162
Вес: 0.44 кг.
Дата издания: 2020
Язык: English
Издание: 1st ed. 2020
Иллюстрации: 75 tables, color; 4 illustrations, color; 26 illustrations, black and white; xii, 162 p. 30 illus., 4 illus. in color.
Размер: 234 x 156 x 11
Читательская аудитория: Professional & vocational
Основная тема: Engineering
Ссылка на Издательство: Link
Рейтинг:
Поставляется из: Германии
Описание:

This book covers various aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems. It gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling for NoC-based multicores. The authors describe the use of the Integer Line Programming (ILP) technique for smaller benchmarks and a Particle Swarm Optimization (PSO) to get a near optimal mapping and test schedule for bigger benchmarks. The PSO-based approach is also augmented with several innovative techniques to get the best possible solution. The tradeoff between performance (communication or test time) of the system and thermal-safety is also discussed, based on designer specifications.

Provides a single-source reference to design and test for circuit and system-level approaches to (NoC) based multicore systems;
Gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling in (NoC) based multicore systems;
Organizes chapters systematically and hierarchically, rather than in an ad hoc manner, covering aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems.

Дополнительное описание: Introduction to Network-on-Chip Designs and Tests.- Iterative Mapping with Through Silicon Via (TSV) placement for 3D-NoC-based multicore systems.- A constructive Heuristic for integrated mapping and TSV Placement for 3D-NoC-based multicore systems.- Disc

Design and Test Strategies for 2D/3D Integration for NoC-based Multicore Architectures, Kanchan Manna; Jimson Mathew